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1 ?2016 integrated device technology, inc revision b august 24, 2016 general description the 8s89833 is a high speed 1-to-4 differential-to-lvds fanout buffer with internal termination. the 8s89833 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the in ternally terminated differential input and v ref _ ac pin allow other differential signal families such as lvpecl, lvds, and cml to be easil y interfaced to the input with minimal use of external components. the device also has an output enable pin which may be useful fo r system test and debug purposes. the 8s89833 is packaged in a small 3mm x 3mm 16-pin vfqfn package which makes it ideal for use in space-constrained applications. features ? four differential lvds outputs ? in, nin input pair can accept the fo llowing differential input levels: lvpecl, lvds, cml ? output frequency: 2ghz ? cycle-to-cycle jitter, rms: 3.5ps (maximum) ? additive phase jitter, rms: 0.03ps (typical) ? output skew: 30ps (maximum) ? part-to-part skew: 200ps (maximum) ? propagation delay: 600ps (maximum) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 8s89833 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment 50 50 dq q0 nq0 q1 nq1 q2 nq2 q3 nq3 in v t nin v ref_ac en pullup 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 q0 n q0 q1 n q1 in v t v ref_a c nin q2 n q2 v dd en q3 v dd gn d nq 3 8s89833 data sheet low skew, 1-to-4 differential-to-lvds fanout buffer w/internal termination
2 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output differential output pair. normally terminated with 100 ? across the pair. lvds interface levels. 3, 4 q1, nq1 output differential output pair. normally terminated with 100 ? across the pair. lvds interface levels. 5, 6 q2, nq2 output differential output pair. normally terminated with 100 ? across the pair. lvds interface levels. 7, 14 v dd power power supply pins. 8 en input pullup synchronizing output enable pin. when lo w, disables outputs. when high, enables outputs. internally connected to a 37k ? pullup resistor. lvttl / lvcmos interface levels. 9 nin input inverting differential lvpecl clock input. rt = 50 ? termination to v t . 10 v ref_ac output reference voltage for ac-coupled applications. equal to v dd - 1.4v (appro x.). maximum sink/source current is 2ma. 11 v t input input termination center-tap. each side of the differential input pair terminates to a v t pin. the v t pins provide a center-tap to a terminati on network for maximum interface flexibility. 12 in input non-inverting differential clock input. rt = 50 ? termination to v t . 13 gnd power power supply ground. 15, 16 q3, nq3 output differential output pair. normally terminated with 100 ? across the pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units r pullup input pullup resistor 37 k ?
3 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet function tables table 3. control input function table note 1: on the next negative tran sition of the input signal (in). figure 1. en timing diagram inputs outputs in nin en q[0:3] nq[0:3] 011 0 1 101 1 0 x x 0 disabled low note 1 disabled high note 1 t pd t s t h v od v dd /2 v dd /2 v in en nin in nqx qx
4 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these condition s or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma input current, in, nin 50ma v t current, i vt 100ma input sink/source, i ref_ac 2ma operating temperature range, t a -40c to +85c package thermal impedance, ? ja , (junction-to-ambient) 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.0 3.3 3.6 v i dd power supply current 100 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd = v in = 3.6v 10 a i il input low current v dd = 3.6v, v in = 0v -150 a
5 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet table 4c. differential dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note 1: guaranteed by design. table 4d. lvds dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c symbol parameter test conditi ons minimum typical maximum units r diff_in differential input resistance (in, nin) 80 100 120 ? r in input resistance in-to-vt 40 50 60 ? v ih input high voltage (in, nin) 1.2 v dd v v il input low voltage (in, nin) 0 v ih ? 0.15 v v in input voltage swing 0.15 1.2 v v diff_in differential input voltage swing 0.3 v v ref_ac bias voltage v dd ? 1.44 v dd ? 1.38 v dd ? 1.32 v i in input current; note 1 in-to-vt 35 ma symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 v v os offset voltage 1.2 1.4 1.6 v ? v os v os magnitude change 50 mv
6 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters characterized at ? 1.4ghz unless otherwise noted. note 1: measured from the differen tial input crossing point to the differential output crossing point. note 2: defined as skew between outputs at the sa me supply voltage and with equal load conditions. measured at the output differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between ou tputs on different devices operat ing at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 5: tested at ? ? 750mhz. note 6: the cycle-to-cycle jitter is dependent on the input source and measurement equipment. symbol parameter test conditions minimum typical maximum units f out output frequency 2ghz t pd propagation delay, (differential); note 1 in-to-qx 400 600 ps t sk(o) output skew; note 2, 3 30 ps t sk(pp) part-to-part skew; note 3, 4 200 ps t jit(cc) cycle-to-cycle jitter, rms; note 5, 6 3.5 ps t jit buffer additive jitter; rms; refer to additive phase jitter section ? = 622.08mhz, integration range: 12khz - 20mhz 0.03 ps ? ? 156.25mhz, integration range: 12khz - 20mhz 0.25 ps t s clock enable setup time en to in/nin 300 ps t h clock enable hold time en to in/nin 500 ps t r / t f output rise/fall time 20% ? 80% 75 200 ps
7 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10khz ? 6.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". additive phase jitter @ 622.08mhz 12khz to 20mhz = 0.03ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
8 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet parameter measureme nt information lvds output load ac test circuit part-to-part skew cycle-to-cycle jitter, rms differential input level output skew propagation delay scope qx nqx 3.3v0.3v power supply +? float gnd v dd nqx qx nqy qy t sk(pp) p art 1 p art 2 nq[0:3] q[0:3] t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nin in v dd gnd v ih cross points v in v il qx nqx qy nqy t pd nq[0:3] q[0:3] nin in
9 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet parameter measure ment information, continued single-ended & differential input voltage swing offset voltage setup output rise/fall time differential output voltage setup v in v diff_in differential voltage swing = 2 x single-ended v in 20% 80% 80% 20% t r t f v od nq[0:3] q[0:3]
10 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet applications information 3.3v differential input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml and other differential signals. both differential signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driv er types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination reco mmendation. please consult with the vendor of the driver component to confirm the dr iver termination requirements. figure 2a. in/nin input with built-in 50 ? driven by an lvds driver figure 2c. in/nin input with built-in 50 ? driven by a cml driver with open collector figure 2b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 2d. in/nin input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup recommendations for unused output pins outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. c1 c2 vt v_ref_ac 50 50 3.3v cml with built-in pullup 3.3v in nin 3.3v receiver with built-in 50 zo = 50 zo = 50
11 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) lvds driver termination a general lvds interface is shown in figure 4. standard termination for lvds type output structure requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds complia nt devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in fi gure x can be used with either type of output structur e. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type st ructure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers s hould be verified for compatibility with the output. figure 4. typical lvds driver termination solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via 100 ? + 100 differential transmission line lvds driver lvds receiver
12 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8s89833. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8s89833 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 0.3v = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.63v * 100ma = 363mw ? power dissipation for internal termination r t power (r t ) max = (v in_max ) 2 / r t_min = (1.2v) 2 / 80 ? = 18mw total power_ max = 363mw + 18mw = 381mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad dire ctly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.381w * 74.7c/w = 113.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
13 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for 8s89833 is: 353 this device is pin and function compatib le and a suggested replacement for 889833. ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 74.7c/w 65.3c/w 58.5c/w
14 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet package outline and package dimensions package outline - k suffix for 16 lead vfqfn table 8. package dimensions reference document: jedec publication 95, mo-220 jedec variation: veed-2/-4 all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 4 d & e 3.00 basic d2 & e2 1.00 1.80 e 0.50 basic l 0.30 0.50 top vie w index a re a d cham fer 4x 0.6 x 0.6 max optional a 0. 0 8 c c a3 a1 seating plan e e2 e2 2 l (n -1)x e (r e f.) (ref. ) n & n eve n n e d2 2 d2 (ref.) n& n od d 1 2 e 2 (typ.) if n & n are eve n (n -1)x e (re f.) b thermal bas e n de d de de e anvil singulation or sawn singulation n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1)
15 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8S89833AKILF 833a ?lead-free? 16 lead vfqfn tube -40 ? c to 85 ? c 8S89833AKILFt 833a ?lead-free? 16 lead vfqfn 2500 tape & reel -40 ? c to 85 ? c
16 ?2016 integrated device technology, inc revision b august 24, 2016 8s89833 data sheet revision history revision date description of change august 24, 2016 datasheet revision b ? table 4c differential dc characteristics table, typo correction: ?v il row, maximum spec changed from v in - 0.15v to v ih - 0.15v. ? deleted ?i? suffix from the part number. february 8, 2016 datasheet revision a ? removed ics from part number where needed. ? removed lf note below ordering information table. ? updated header and footer.
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8s89833 data sheet

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